1. Field of the Invention
The present invention is directed generally to dynamic random access memory cells, and, more particularly, to dynamic random access memory cells with a junction device in the storage unit to reduce leakage from the storage unit.
2. Description of the Background
Dynamic random access memory (DRAM) devices have become widely accepted in the semiconductor industry. DRAM""s typically cost less to produce than other types of memory devices due to their relative simplicity.
At a fundamental level, a DRAM memory cell, or memory bit, consists of one transistor and on-capacitor. When the transistor and capacitor are fabricated on a semiconductor substrate, a number of junctions between adjacent materials are formed. Junctions may be classified as homojunctions or heterojunctions. Homojunctions are junctions formed by doping a uniform body of semiconductor material. Thus, doped material adjacent to undoped material, or two adjacent areas of material that are doped differently from one another, form homojunctions. Heterojunctions are formed by two different semiconductor materials which are adjacent.
One way to understand a junction is to examine the electron energy band diagram for the junction. Such a diagram illustrates the energy band levels of the materials of the junction with the potential barrier between the two sides of the junction being indicative of the degree of difficulty an electron will have in traveling from one side to the other. The larger the barrier, the greater the degree of difficulty.
It is known that the size of the barrier, i.e., the characteristics of the junction, can be varied by the application of electric fields. Thus, under certain circumstances, the barrier may be large while under others the barrier may be small. Those characteristics have enabled heterojunction devices to act as storage devices. See, for example, U.S. Pat. No. 3,740,620 entitled xe2x80x9cStorage System Having Heterojunctionxe2x80x94Homojunction Devicesxe2x80x9d, and U.S. Pat. No. 3,739,356 entitled xe2x80x9cHeterojunction Information Storage Unit.xe2x80x9d
DRAM devices are typically fabricated of homojunctions. To enable a quick read to or write from the memory cell, it is desirable to have a small electron barrier. However, small electron barriers mean high leakage rates, i.e. electrons traveling across the barrier when they aren""t supposed to. Thus, there is an engineering tradeoff between speed and leakage rates.
DRAM cells of the prior art all exhibit charge leakage such that the information stored in the cell must be periodically refreshed. The more often the cell is refreshed, the slower the memory operates and the more power it consumes. High frequency refresh operations also introduce noise into the array. Thus, the need exists for a DRAM memory circuit that has reduced charge leakage from the storage node. That translates into a lower refresh frequency, higher operating speeds, and lower power consumption.
The present invention, according to its broadest implementation, is directed to a memory cell which incorporates a diode between a switching device and a storage node to reduce charge leakage from the storage node.
The present invention also contemplates a solid state memory cell which comprises a storage capacitor, a transistor, and a junction fabricated between the storage capacitor and the transistor. The present invention further contemplates an array of such memory cells comprised of a plurality of column lines and row lines interconnecting the memory cells and a plurality of sense amplifiers and precharge circuits connected between the column lines.
The present invention may also be part of a complete memory device which itself may be part of a system. The system may comprise a processor, read and write control logic, a plurality of memory cells, a plurality of column lines and row lines interconnecting the plurality of memory cells, and a plurality of sense amplifiers and precharge circuits connected between the column lines.
The present invention also contemplates a method of controlling charge transfer to and from a storage node through a switching device.
The present invention represents a substantial advance over prior memory cells and methods of controlling charge transfer to and from a storage node through a switching device. Because the present invention incorporates a diode between the switching device and the storage node, the leakage from the storage node is reduced and memory refresh frequency is reduced. Those advantages and benefits of the present invention, and others, will become apparent from the Detailed Description of the Invention hereinbelow.